1. Field of the Invention
The present invention concerns a method for determining a logic state of a memory cell in a data storage device, wherein said cell stores data in the form of an electrical polarization state in a capacitor containing a polarizable material, wherein said polarizable material is capable of maintaining a non-vanishing electrical polarization in the absence of an externally impressed voltage across said capacitor, and of generating a current response to an applied voltage, said current response comprising linear and non-linear components. The present invention also concerns a first apparatus for performing a phase comparison in a method according to the invention wherein the apparatus comprises a signal generator for supplying a read signal with given frequency to a memory cell, wherein the memory cell in response to the read signal outputs a response component at twice the given phase of the read signal; as well as a second apparatus for performing a phase comparison in the method according to the invention, wherein the apparatus comprises a signal generator for supplying two or more read signals with given phases to a memory cell, wherein the memory cell in response to said read signals outputs a response signal having two or more non-linear current components.
Particularly the present invention concerns a non-destructive readout of memory cells, wherein the polarizable material exhibits hysteresis, notably an electret or a ferroelectric material, as known in the art.
2. Description of Related Art
During recent years, data storage has been demonstrated in electrically polarizable media consisting of thin films of ceramic or polymeric ferroelectrics. A major advantage of such materials is that they retain their polarization without the permanent supply of electrical energy, i.e. the data storage is non-volatile.
Two main classes of memory devices have been demonstrated where the logic state of an individual memory cell is represented by the polarization direction of the ferroelectric thin film in that cell. In both cases data are written into the memory cells by polarizing the film in the desired direction through the application of an appropriately directed electrical field exceeding the coercive field of the ferroelectric. However, device architectures are fundamentally different:
In the first class of devices, each memory cell incorporates at least one transistor. The overall memory architecture is of the active matrix type, the major advantage compared with traditional SRAM and DRAM devices being the non-volatile nature of the ferroelectrically stored logic state.
One broad sub-class of such ferroelectric-based memory devices, commonly termed FeRAM or FRAM (a Symetrix copyrighted term), is extensively described in the scientific and patent literature and is presently being commercialized by a number of companies worldwide. In its simplest form (1T-1C architecture), each FeRAM memory cell has a single transistor and capacitor as illustrated in FIG. 1, where the capacitor contains a ferroelectric which can be polarized in one or the other direction, representing a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, respectively. A given memory cell is written, i.e. prepared with the ferroelectric capacitor polarized in the desired direction, by applying appropriate voltages to the wordline, bitline and driveline serving that cell. Reading is performed by floating the bitline and applying a positive voltage to the driveline while asserting the wordline. Depending on the direction of polarization in the capacitor, i.e. whether the cell stores a logic xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d, the charge transferred to the bitline in this process shall be either significant or small, and the logic state of the cell is determined by recording the magnitude of this charge. Since this read operation is destructive, the data must be written back afterwards to avoid permanent loss of stored information. A large number of patents have been issued on variants of the basic FeRAM concept, see, e.g. U.S. Pat. No. 4,873,664 (Ramtron International Corp.), U.S. Pat. No. 5,539,279 (Hitachi, Ltd), U.S. Pat. No. 5,530,668 (Ramtron International Corp), U.S. Pat. No. 5,541,872 (Micron Technology), U.S. Pat. No. 5,550,770 (Hitachi, Ltd), U.S. Pat. No. 5,572,459 (Ramtron International Corp), U.S. Pat. No. 5,600,587 (NEC Corp.), U.S. Pat. No. 5,883,828 (Symetrix Corp.). The patents address both circuit architectures and materials, reflecting difficult problems that have hindered practical implementation of ferroelectric memories since their conceptual introduction decades ago. Thus, the destructive read aspect of these memories has comported fatigue in the ferroelectric materials used, limiting the operational lifetime and thus basic usability for large classes of applications. Following intensive efforts, certain materials (e.g. PZT and SBT) have been refined and modified so as to sustain the large number of switching cycles (10 exp 10 to 10 exp 14) of relevance in the most demanding applications, as well as exhibiting adequate resistance to imprint, etc. However, these optimized materials require annealing at high temperatures, are vulnerable to hydrogen exposure, etc, and generally pose costly and complex problems in connection with integration into high volume production based on established silicon device manufacturing. Further, their requirement for thermal treatment makes them unsuitable for future integration in polymer-based electronic devices. Some of the patents reflect efforts to circumvent drift and manufacturing tolerance problems by making use of more complex architectures. This may include memory cells containing two ferroelectric capacitors and two transistors (2C-2T designs) to allow for referencing cells and circuits and more complex pulsing protocols. It may be noted that at present all ferroelectric memories in production use the 2C-2T architecture, since materials are still lacking that have adequate stability under exposure to time, temperature and voltage cycling (cf.: D. Hadnagy: xe2x80x9cMaking ferroelectric memoriesxe2x80x9d, The Industrial Physicist, pp.26-28 (December 1999)).
In another subclass of devices employing one or more transistors in each memory cell, the source-drain resistance of a transistor in the cell is directly or indirectly controlled by the polarization state in a ferroelectric capacitor in that cell. The basic idea is not new and has been described in the literature (cf., e.g. Noriyoshi Yamauchi, xe2x80x9cA metal-Insulator-Semiconductor (MIS) device using a ferroelectric polymer-thin film in the gate insulatorxe2x80x9d, Jap.J.Appl.Phys. 25, 590-594 (1986); Jun Yu et al., xe2x80x9cFormation and characteristics of Pb(Zr,Ti)O3 buffer layerxe2x80x9d, Appl.Phys.Lett. 70, 490-492 (1997); Si-Bei Xiong and Shigeki Sakai xe2x80x9cMemory properties of SrBi2Ta2O9 thin films prepared on SiO2/Si substratesxe2x80x9d, Appl.Phys.Lett. 70, 1613-1615 (1999)). In U.S. Pat. No. 5,592,409 (Rohlm Co., Ltd.), Nishimura et al. describe a non-volatile memory based on a ferroelectric film which is polarized in one or the other direction, representing a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. The polarized ferroelectric provides bias on the gate of a transistor, thereby controlling the current flow through the transistor. An obvious advantage of this mode of operation is that the logic state of the memory cell can be read non-destructively, i.e. without incurring polarization reversal in the ferroelectric capacitor. A related concept, described by J. T. Evans and J. A. Bullington in U.S. Pat. No. 5,070,385, is based on a semiconductor material in close contact with the ferroelectric. Here, the semiconducting material exhibits an electrical resistance which depends on the state of polarization in the ferroelectric. Unfortunately, there remain severe unsolved materialsxe2x80x94and processing issues in connection with all of the above mentioned concepts (cf., e.g. D. Hadnagy, xe2x80x9cMaking ferroelectric memoriesxe2x80x9d, The Industrial Physicist, pp.26-28 (December 1999)), and their successful commercialization in the foreseeable future is at present doubtful.
In both subclasses referred above, the need for one or more transistors in each cell represents a major disadvantage in terms of complexity and reduced areal data storage density.
In the second class of devices, which is of particular relevance here, memory cells are laid out in a passive matrix architecture where two sets of mutually orthogonal electrodes form arrays of capacitor-like structures at the crossing points between the electrodes. Each memory cell may be created very simply as illustrated in FIG. 2, by employing ribbon-like electrodes that define an overlap region where they cross, the overlap region constituting a sandwich of polarizable material between parallel electrode planes. Alternative capacitor structures are possible, however, where the electrical fields that interact with the polarizable material have major components directed parallel to the substrate rather than perpendicular to it. Such xe2x80x9clateralxe2x80x9d architectures shall not be discussed further here, however, since the particular choice of cell architecture is immaterial to the subject matter of the present invention. According to prior art, the data in individual memory cells are read by applying an electrical field to the material in each cell in question, of sufficient magnitude to overcome the hysteresis effect and align the electrical polarization in the cell in the direction of the applied field. If the material already were polarized in that direction prior to application of the field, no polarization reversal takes place and only a small transient current flows through the cell. If, however, the material had been polarized in the opposite direction, polarization reversal takes place, causing a much larger transient current to flow through the cell. Thus, the logic state, i.e. the direction of the electrical polarization in the individual memory cell, is determined by application of a voltage of magnitude sufficient to exceed the coercive field in the ferroelectric, and detection of the resulting current.
Compared to active matrix based devices, the passive matrix based ones can be made with much higher memory cell density, and the memory matrix itself is much less complex. However, the readout process according to prior art is destructive, involving loss of the data content in the cell that is read. Thus, data that are read must be written back into the memory device if further storage of those data is desired. A more serious consequence of the polarization switching is fatigue, i.e. a gradual loss of switchable polarization which typically is accompanied by a need for higher applied voltage to the cell to effect the polarization reversal. Fatigue limits the number of read cycles that can be sustained by a given memory cell and thus the range of applications. In addition, it leads to slower response and higher voltage requirements for the memory device. The attendant gradual variation in the operation parameters for individual memory cells in a given device cannot be predicted a priori and leads to a need for xe2x80x9cworst casexe2x80x9d design and operation which is sub-optimal.
Efforts have been made to develop techniques that allow non-destructive readout from ferroelectric-based memories while maintaining simple elementary memory cell architecture. Thus, C. J. Brennan describes ferroelectric capacitor cells and associated elementary circuit modules for data storage in U.S. Pat. Nos. 5,343,421; 5,309,390; 5,262,983; 5,245,568; 5,151,877 and 5,140,548. By probing the small-signal capacitance values while simultaneously subjecting the ferroelectric to moderate bias fields, i.e. bias fields that do not lead to the peak voltage across the cell during read-out exceeding the coercive field in the ferroelectric, the direction of the spontaneous polarization in the capacitor and thus the logic state of the memory cell is determined. However, there are certain very specific premises for applying the methods and apparatus as described by Brennan, invoking phenomena based on space charge accumulation at the electrodes which is explicitly dependent on the materials used in the electrodes and the adjoining ferroelectric. Readout of data involves probing of the space charge, which must be performed on time scales that are compatible with such charge accumulation. Furthermore, Brennan""s patents contain no teachings on how the small-signal and biasing voltages shall be timed and correlated in relation to each other, which is of paramount importance for implementation in practical devices. The above mentioned U.S. Pat. No. 5,140,548 describes a device which does not require bias from an external source, deriving an internal bias from a contact potential difference between the electrodes sandwiching the ferroelectric core. While elegant in principle, this solution suffers from serious drawbacks when faced with the task of implementations in practical devices. Thus, the predictability and control that can be achieved by external biasing is sacrificed, being replaced by a fixed bias which is explicitly dependent on materials purity and processing conditions as well as operating temperature. The unipolar and continuous nature of the internally generated bias promotes imprint in the ferroelectric, a well-known and highly undesirable phenomenon in ferroelectric memory devices. Finally, a fixed bias is of little or no value when implementing correlation strategies as taught in the present document.
Thus, there is a need for devices and methods whereby data can be read non-destructively from simple memory cells in the form of capacitors that are filled with an electrically polarizable material exhibiting hysteresis, which cells not being dependent on containing active circuit elements such as transistors. This need is particularly acute in passive matrix addressed memory structures with ferroelectric capacitors.
It is a major object of the present invention to provide a conceptual basis for non-destructive read-out of data from data storage devices containing cells with electrically polarizable media, in particular ferroelectrics.
By extension of the above, it is another object of the invention to permit read-out of data without incurring the fatigue and wear that accompany the traditional read-out by polarization switching and which limits the usable life span of memory devices based on ferroelectrics. Further it is an object of the invention to obviate the need for restoring the data content of cells that have been read, which is required in destructive readout techniques, and thus to simplify the readout protocol and reduce the hardware complexity.
It is a further object of the invention to enhance the reliability in the readout process by providing more than one discrimination criterion for determination of logic state in a given memory cell.
Finally, it is also an object of the present invention to describe generic procedures and hardware to implement such non-destructive read-out of data.
The above objects as well as additional features and advantages are achieved with a method according to the present invention, which is characterized by steps for applying a time dependent small-signal voltage over the capacitor, said small-signal voltage having an amplitude and/or duration less than that required for causing a significant permanent change in the polarization state of the capacitor, and recording at least one component of a generated small-signal current response over the capacitor, said at least one component having either a linear or non-linear relationship to said small-signal voltage, whereby said logic state is determined by at least one parameter, being a characteristic of said at least one recorded component, the determination of the logic state taking place by temporal correlation between said small-signal voltage and said at least one recorded component, and subject to a predetermined protocol.
In the method according to the invention it is advantageous applying the small-signal voltage superimposed on a quasi-static voltage of either polarity across said capacitor and then the quasi-static voltage may have either polarity or may be switched between a set of positive and/or negative values.
In the method according to the invention it is also advantageous applying said small-signal voltage superimposed on a low frequency or slowly varying voltage across the capacitor, said small-signal and said low frequency or slowly varying voltages in sum having an amplitude and/or duration less than that required for causing a significant permanent change in the polarization state of the capacitor, and then it is preferable recording a non-linear component of the current response to said small-signal voltage and correlating said non-linear component with said slowly varying voltage.
In a first advantageous embodiment of the method according to the invention the small signal voltage is selected as being periodic with a dominant Fourier component at frequency xcfx89, the phase of the 2nd harmonic component of the current response is recorded, and the phase is compared with a reference phase derived from said time-dependent voltage impressed on the capacitor. In this connection the small-signal voltage can then preferably be selected as sinusoidal.
In a second advantageous embodiment of the method according to the invention the time-dependent small-signal voltage is selected as the sum of two periodically varying components with dominant Fourier components at frequencies xcfx891 and xcfx892, respectively, the phases of the components of said current response at the sum and difference frequencies xcfx891+xcfx892 and xcfx891xe2x88x92xcfx892, is recorded, and the phases are compared with a reference phase derived from the time-dependent voltage impressed on the capacitor. In this connection the periodically varying voltage components can then be selected as sinusoidal.
In the latter case it is considered advantageous recording the phases of two or more of the non-linear current response components, at 2xcfx891 and/or 2xcfx892 and/or xcfx891+xcfx892 and/or xcfx891xe2x88x92xcfx892, and comparing said with a reference phase derived from said time dependent voltage impressed on the capacitor, or alternatively recording the phases of two or more of the non-linear current response components, at 2xcfx891 and/or 2xcfx892 and/or xcfx891+xcfx892 and/or xcfx891xe2x88x92xcfx892, and comparing the phases with a reference phase derived from a reference cell of known logic state that is subjected to the same driving voltages.
In a third advantageous embodiment of the method according to the invention the time-dependent small-signal voltage is superimposed on a biasing voltage of amplitude less than that required for causing significant, permanent change in the polarization state in the capac or, the first derivative of the non-linear current response to the time-dependent voltage is recorded as deduced via the small-signal current response to the time-dependent voltage, and the value of the first derivative is correlated with the magnitude and/or phase of the biasing voltage. In this connection the biasing voltage can then be selected as a DC offset voltage.
In the latter case the biasing voltage can be selected as a DC offset voltage which preferably is varied between a set of predetermined positive and/or negative values and then preferably periodically between a positive and a negative value.
In the third embodiment of the invention the biasing voltage can also be selected as a smoothly varying voltage sweeping a voltage range between two positive values or two negative values or a positive and a negative value. In this connection the biasing voltage can be swept periodically at a frequency lower than the time-dependent voltage, or the biasing voltage can be selected as varying sinusoidally with time.
Finally, in the method according to the present invention it is considered advantageous that the predetermined protocol assigns the logic state either of two logic values dependent on the value of the at least one parameter.
The above objects as well as additional features and advantages are also realized with an apparatus according to the invention which is characterized in comprising a phase-sensitive detector and discriminator connected with a memory cell for receiving one or more response signals therefrom and via a reference source with the signal generator for receiving a phase reference for the read signal input to the memory cell, said phase reference being applied as a reference in the phase sensitive detector and discriminator for determining a logic state of the memory cell by means of a phase comparison.
Finally, the above objects as well as additional features and advantages are also realized with another apparatus according to the invention which is characterized in comprising a phase sensitive detector connected with a memory cell and adapted for performing a phase sensitive detection of at least two phases in the response signal output from a memory cell, a reference source connected with said signal generator and adapted for generating phase references from the sum and differences of the phases detected in the response components, to the phase sensitive detector connected therewith, and a discriminator/logic circuit being connected with former for receiving the output thereof in the form of a phase comparison performed therein and adapted for determining a logic state of the memory cell.
In a preferred embodiment of this apparatus an xcfx89+xcfx80 phase shifter is connected with the reference source for receiving the output thereof and delivering the xcfx89+xcfx80 phase-shifted output to the phase sensitive detector and optionally also to the discriminator and logic circuit.